MS663 Multi physics chip-package-board co-design

J. Reisinger1, undefinedK. Pressel2
1Infineon Technologies Austria AG/AT, 2Infineon Technologies AG/DE


The Mini-Symposium “Multi Physics Chip-Package-Board Co-Design” is intended to address the enormous increases of complexities and interdependencies in system hardware design methodologies and related automation design tools. Because of this increases, there is no longer the chance to execute most of the design tasks sequentially, as it had been done successfully before. Furthermore, because of the ongoing reduction of feature sizes (technology shrinks at all implementation domains: chip, package, board) the interoperability & interference between functional components will be a major focus of the proposed Symposium.


Throughout this Mini-Symposium, design methodologies, tool solutions and existing gaps (including roadmaps to close them) will be presented by 3 groups of speakers. One group will demonstrate the position of some of the market leading vendors of EDA Tools (Electronic Design Automation) like Cadence, Sigrity, COMSOL, DOCEA. The second one is a group of users, which will show the mapping (mismatch?) between vendor’s view and user’s expectations (Infineon Chip Design as well as Package Design Methodology Team will contribute, but also methodology experts from ST-Microelectronic did confirm their participation).
In addition to the vendor and the user group, there is the plan to have room for the academia
(e.g. FhG is committed).


As summarized in the Symposium’s title, three of the major fields of hardware engineering complexities will be addressed:

  1. Multi Physics Design in this context means the interaction between the electrical design (dealing with voltages, currents, electromagnetic fields, …) – the thermal design (covering aspects of power & heat distribution) – and the mechanical design which is not only addressing the physical outline of the product to be designed, but also the mechanical stress conditions which apply on the product materials, mainly the interfaces between those materials and related effects with impact on disciplines mentioned.
  2. Chip-Package-Board Design Methodology and Tooling presentations will be presented looking at three complexity views. First differentiating view is related to the CAD tools which appear totally different for Chip, Package and/or PCB Design tasks. Those Tools are offered by different EDA-Vendors. Most of the “big” leading vendors claim to cover all views – we expect good discussions between the joining tool vendors and the group of users, including academia and the auditorium.
    The second aspect (view) is defined by the differentiation between the skills and expertise of engineers doing the design jobs. E.g. a Chip-Designer knows well how to synthesize a Chip Layout from given lists of components and a connectivity definition, but this designer has no glue on how to place and route IC-sockets on a PCB (Printed Circuit Board). On the other hand, a PCB-Designer, who could do this job very well, does not know how to design or even modify a Package for the Chip – and so on. Additionally, in most cases those different Engineering Teams are working in different companies, locations even continents. A significant question in the Symposium will be on how the EDA tools have to look like, that the different named engineering communities are able to use them efficiently.
    Last but not least, the requirements on chip, package and board design data management have to be handled as the third view of complexity under discussion. Especially ideas to use joint, multiparty data management systems within different companies will be thrashed out.
    E.g. communication systems, accessibility for Multi Physics Design aspects and parameters, connections and links to parameters, tech databases available on the market.
  3. Well synchronized Co-Design instead of sequential execution of Chip, Package, Board design tasks asks for optimized, well linked design processes (design flows) enabling Multi Physics Design also. It has to be guaranteed that mainly each output of a design task can be used as an input for successor design task without suffering from data loss or errors due to manual steps (e.g. output or changes of Chip-Layout-Generation => become input for PCB parasitic extraction).


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